1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material including a cap layer acting as an efficient diffusion barrier layer for the metal.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per chip.
In integrated circuits having minimum dimensions of approximately 0.35 μm and less, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 0.1 μm and significantly less, it turns out, however, that the signal propagation delay is no longer limited by the field effect transistors but is limited, owing to the increased circuit density, by the interconnect lines, since the parasitic line-to-line capacitance (C) is increased and the conductivity (1/R) of the lines is reduced due to their reduced cross-sectional area. The parasitic RC time constants therefore require the introduction of a new type of materials for forming the metallization layers of advanced semiconductor devices.
Traditionally, metallization layers have been and still are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities than may be necessary in integrated circuits having extremely scaled feature sizes, aluminum is being replaced by copper, which has a significantly lower electrical resistance and a higher resistivity against electromigration. For highly sophisticated applications, in addition to using copper and/or copper alloys, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>5) may be replaced by so-called low-k dielectric materials. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a copper-based metallization layer, possibly in combination with a low-k dielectric material, is associated with a plurality of issues to be dealt with.
For example, copper may not be deposited in relatively high amounts in an efficient manner by well-established deposition methods, such as chemical and physical vapor deposition. Moreover, copper may not be efficiently patterned by well-established anisotropic etch processes. Therefore, the so-called damascene or inlaid technique is frequently employed in forming metallization layers including copper lines. Typically, in the damascene technique, the dielectric layer is deposited and then patterned to receive trenches and vias that are subsequently filled with copper or alloys thereof by plating methods, such as electroplating or electroless plating. Forming copper-based metallization layers in standard dielectric materials, such as silicon dioxide, and a plurality of low-k dielectrics is presently frequently being practiced by providing a dielectric diffusion barrier layer on top of the copper-based region as copper readily diffuses in a plurality of dielectrics, such as silicon dioxide and many low-k dielectrics. Moreover, the diffusion of moisture and oxygen into the copper-based metal has to be suppressed as copper readily reacts to form oxidized portions, thereby possibly deteriorating the characteristics of the copper-based metal line with respect to adhesion, conductivity and the resistance against electromigration. For instance, silicon nitride is known as an effective copper diffusion barrier and may be used as a cap layer. In other cases, when the moderately high permittivity of silicon nitride is considered inappropriate, nitrogen enriched silicon carbide (SiCN) is frequently used as a copper diffusion barrier.
Despite the diffusion hindering effect of the silicon nitride cap layers and silicon carbide based cap layers, it turns out, however, that copper's resistance against electric current induced material transport (electromigration) strongly depends on the characteristics of an interface between the copper-based metal and the adjacent cap layer. Electromigration is a phenomenon that mainly occurs in highly scaled electronic devices having metal lines which are embedded into a dielectric material, thereby providing a high heat dissipation capability and thus the possibility to operate at extremely high current densities of up to several kA per cm2. At respective high current densities, the directed electron motion of the current flow may result in a significant momentum transfer to the metal atoms, thereby generating a mass flow in the direction of the moving electrons, which may finally cause voids and hillocks upstream and downstream, respectively, of respective metal areas. Hence, the lifetime of semiconductors may strongly depend on the electromigration behavior of the metallization structure of the device. Generally, it would be possible to form virtually “immortal” metallization structures, which would, however, significantly reduce design flexibility and also scalability of modern semiconductor devices. The general trend in the market of electronic devices, however, demands reduced device dimensions and increased performance, thereby rendering the increase of the resistance against electromigration induced line degradation an important factor for forming advanced semiconductor devices. Since electromigration is an interaction of electrons and metal atoms, which results in a directed “diffusion” of metal atoms, the number and quality of the metal internal diffusion paths, such as grain boundaries, and in particular the diffusion paths at interfaces may strongly affect the overall electromigration performance of metallization structures. Hence, it is important to create stable interfaces when confining the metal, such as copper and copper alloys, by appropriate barrier materials. Therefore, in sophisticated integrated circuits featuring high current densities, it is generally preferable to design the deposition process for the capping layer such that a desired high adhesion and thus high performance with respect to electromigration is achieved. For this purpose, corresponding deposition techniques with preceding plasma-based cleaning steps are typically used. With reference to FIGS. 1a-1b, a typical conventional process flow for forming a SiCN cap layer will now be described in more detail.
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 prior to the formation of a silicon nitride or a nitrogen enriched silicon carbide based cap layer on a copper-containing metal region. The semiconductor device 100 comprises a substrate 101 that may include circuit elements, such as transistors, capacitors and the like, which for convenience are not shown. Moreover, the substrate may have formed thereon one or more metallization layers, i.e., dielectric layers in which are embedded metal filled lines and vias so as to establish the required electrical connections between the individual circuit elements. For convenience, a single copper based metal region 103 is illustrated so as to represent any copper based metal lines of one or more metallization layers. The copper based metal region 103 may be embedded in any appropriate dielectric material, such as silicon dioxide, fluorine doped silicon dioxide, a low-k material such as hydrogen enriched silicon oxycarbide (SiCOH), or any combination thereof. As previously explained, the copper may readily diffuse in a plurality of dielectric materials and hence a conductive barrier layer 102 is typically provided between the dielectric material of the substrate 101 and the copper-containing material of the region 103. The barrier layer 102 may be comprised of two or more individual layers so as to provide the required characteristics not only in view of the copper diffusion blocking effect, but also with respect to adhesion to the surrounding material and the like. For example, tantalum, tantalum nitride, titanium, titanium nitride and combinations thereof are frequently used as appropriate materials for the barrier layer 102.
A typical process flow for forming the semiconductor device 100 as shown in Figure may comprise the following processes. After the formation of any circuit elements, which may exhibit extremely scaled critical dimensions in sophisticated applications, such as a gate length of field effect transistors in the range of approximately 50-100 nm and less, one or more metallization layers may be formed in accordance with well-established single damascene or dual damascene techniques. That is, an appropriate dielectric layer stack including an etch stop/barrier layer similar to the cap layer that is to be formed on top of the copper based metal region 103 may be deposited followed by another dielectric layer, such as silicon dioxide or a low-k dielectric material, which may be formed by well-established techniques, such as plasma enhanced chemical vapor deposition (PECVD), spin-on techniques and the like. Thereafter, the dielectric layer stack may be patterned by photolithography and etch techniques to form trenches and vias in the dielectric layer stack, wherein the lower etch stop/barrier or cap layer (not shown) may be used as an etch stop. For convenience, only a single trench may be considered for the further description, in which the copper based metal region 103 is to be formed. Thus, after the patterning of the corresponding trench, the barrier layer 102 may be deposited on the basis of well-established deposition techniques, such as sputter deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD) and the like. For instance, well-established recipes for the sputter deposition of tantalum and tantalum nitride as well as titanium and titanium nitride may be used to form the barrier layer 102 having the desired characteristics. Thereafter, a seed layer (not shown) comprised of, for instance, copper may be formed by sputter deposition or any other appropriate deposition technique. Based on the seed layer, a copper based material, such as pure copper, a copper alloy or any combination thereof, may be deposited by, for instance, electroplating, thereby reliably filling the previously formed trenches and vias and also forming the copper based metal region 103. Next, excess material deposited during the preceding electrochemical deposition process, as well as the seed layer and the conductive barrier layer 102 formed on portions outside the copper based metal region 103, may be removed to provide the electrically insulated copper based metal region 103. For this purpose, a removal process typically comprising a chemical mechanical polishing (CMP) process may be performed, during which a surface 103A of the region 103 is exposed, which may thus be subjected to any chemical reactions, resulting in discolored and eroded or oxidized portions on the surface 103A, since copper may readily react with moisture, oxygen, fluorine and other traces of gases that may typically be encountered during the removal of the excess material and subsequent substrate handling processes. Consequently, prior to the formation of an insulating cap layer, which may also act as an etch stop layer for the formation of any further metallization layers on top of the substrate 101, the surface 103A is typically cleaned in order to enhance conductivity and the adhesion characteristics and thus the electromigration behavior of the region 103 due to enhanced interface characteristics with respect to a dielectric cap material still to be formed. To this end, a plasma based treatment may be performed to efficiently remove oxidized, discolored and eroded portions from the surface 103A while at the same time substantially avoiding a reformation of these portions. For example, a plasma ambient 104 may be established on the basis of ammonia (NH3) and nitrogen (N2), wherein the plasma ignition is typically performed on the basis of radio frequency (RF), the power density of which may significantly determine, in combination with the gas flows of ammonia and nitrogen, the effectiveness of the plasma treatment 104. For instance, with appropriately selected gas flows in the range of approximately 500-600 sccm (standard cubic centimeter per minute) and 6000 sccm for ammonia and nitrogen, respectively, and an RF power of 200 watts for a plasma deposition chamber, such as the Producer™ available from Applied Materials Corporation, a good adhesion for a nitrogen enriched silicon carbide (SiCN) layer may be obtained. After the plasma treatment 104, the ambient may be changed by applying appropriate precursor materials so that an appropriate deposition atmosphere may be established in situ, thereby avoiding undue discoloration and oxidation on the exposed surface 103A. After a corresponding stabilization step for introducing the precursor gases, such as 3MS (tri-methylsilane) and ammonia for forming a nitrogen enriched silicon carbide layer, an appropriate RF power may be supplied to establish a corresponding plasma, thereby initiating the deposition process.
FIG. 1b schematically shows the semiconductor device 100 during this deposition step, wherein, on the basis of the plasma 105 containing 3MS, NH3 and He, a cap layer 106 comprised of nitrogen enriched silicon carbide (SiCN) is formed above the substrate 101 and on the exposed surface 103A, thereby creating a corresponding interface, which is, for convenience, also referred to as 103A. Thereafter, further processing may be continued by forming further metallization layers, wherein the cap layer 106 may act as an etch stop layer for patterning a corresponding dielectric layer stack for forming corresponding vias and trenches.
During the operation of the device 100, the current-induced material transport, also referred to as electromigration, at the interface 103A may nevertheless reach critical values, especially when a copper based metal region 103 is part of a higher metallization layer. Thus, for sophisticated applications requiring increased current densities, it has been proposed to form an increased amount of copper silicide based compounds (CuSi) at the interface with the following dielectric barrier material, since the CuSi may provide enhanced electromigration behavior. However, the controlled creation of CuSi prior to the actual deposition of SiC, SiCN, SiN in situ based on respective efficient plasma-based cleaning processes may be difficult, since the silicon-containing precursor gases may diffuse in a very uncontrolled manner into the copper-containing metal after the plasma cleaning process, in particular at temperatures above 300° C. as are usually used for the deposition, thereby resulting in a substantially non-controllable formation of CuSi, which may have a negative impact on the electrical performance and uniformity during operation of the metallization structure.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.